Lifetime Reliability of Multi-core Systems: Modeling and Applications

Advancements in technology have enabled the integration of a great amount of processor cores on a single silicon die, known as multi-core systems. Quite a few commercial designs have been launched into market in recent years, for example, nVidia 128-core GeForce 8800 GPU [77] and ARM11 PrimeXsys platform [7]. Some research groups even predicted that thousand-core processors would be commercialized in next decade. When we rejoice in the admirable functionality and performance provided by these products, the ever-shrinking feature size is subtly undermining this apparent flourish, posting serious challenges to the silicon integrated circuit (IC) community. The ever-increasing on-chip power and temperature density has significantly accelerated the aging effect induced by permanent failure mechanisms of state-ofthe-art IC products and hence dramatically shortened products’ service life. Thus, it becomes a challenging task for designers to meet multi-core chips’ lifetime reliability requirement. This is not a trivial task: because the aging rate depends on operational temperature, supply voltage, and operational frequency, almost all design-stage decisions and even the system workload affect the reliability stress on processor cores. Needless to say, efficient stress estimation is urgently required by designers. Unfortunately, there is neither natural way nor well-accepted literature on this issue. To tackle this problem, we develop a comprehensive mathematical model that